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RTL8363SB-cg layer 2 managed 2+2-port 10/1 00/1000m switch controller datasheet (confidential: development partners only) rev. 1.0 09 june 2011 track id: jatr-2265-11 realtek semiconductor corp. no. 2, innovation road ii, hsinchu science park, hsinchu 300, taiwan tel.: +886-3-578-0211 fax: +886-3-577-6047 www.realtek.com
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller ii track id: jatr-2265-11 rev. 1.0 copyright ?2011 realtek semiconductor corp. all rights reserve d. no part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of realtek semiconductor corp. disclaimer realtek provides this document ?as is?, without warranty of any kind. realtek may make improvements and/or changes in this document or in the product de scribed in this document at any time. this document could include technical inaccura cies or typographical errors. trademarks realtek is a trademark of realtek semiconductor cor poration. other names mentioned in this document are trademarks/registered trademarks of their respective owners. using this document this document is intended for the hardware and soft ware engineer?s general in formation on the realtek RTL8363SB ic. though every effort has been made to ensure that th is document is current and accurate, more information may have become available subsequent to the production of this guide. revision history revision release date summary 1.0 2011/06/09 first release.
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller iii track id: jatr-2265-11 rev. 1.0 table of contents 1. general desc ription ............................................................................................................ ..................................1 2. features ....................................................................................................................... ..................................................3 3. system applications............................................................................................................ ...................................5 4. application examples ........................................................................................................... ................................5 4.1. 2-p ort 1000b ase -t r outer with d ual mii/rgmii/gmii ....................................................................................5 5. block diagram .................................................................................................................. .........................................6 6. pin assignments ................................................................................................................ .........................................7 6.1. p ackage i dentification ............................................................................................................................... ............7 6.2. p in a ssignments t able ............................................................................................................................... .............8 7. pin descriptions............................................................................................................... ........................................11 7.1. m edia d ependent i nterface p ins .........................................................................................................................11 7.2. g eneral p urpose i nterfaces ............................................................................................................................... .11 7.2.1. gmii interface pins............................................................................................................ ..................................11 7.2.2. rgmii pins..................................................................................................................... ......................................14 7.2.3. mii pins................................................................................................................................................................16 7.3. led p ins ............................................................................................................................... ....................................19 7.4. c onfiguration s trapping p ins .............................................................................................................................20 7.5. c onfiguration s trapping p ins (disautoload and dis_8051).....................................................................21 7.6. m anagement i nterface p ins ............................................................................................................................... .21 7.7. m iscellaneous p ins ............................................................................................................................... ................22 7.8. t est p ins ............................................................................................................................... ...................................22 7.9. p ower and gnd p ins ............................................................................................................................... ...............22 8. physical layer functional overview............................................................................................. .........23 8.1. mdi i nterface ............................................................................................................................... .........................23 8.2. 1000b ase -t t ransmit f unction ...........................................................................................................................23 8.3. 1000b ase -t r eceive f unction ..............................................................................................................................2 3 8.4. 100b ase -tx t ransmit f unction ...........................................................................................................................23 8.5. 100b ase -tx r eceive f unction .............................................................................................................................24 8.6. 10b ase -t t ransmit f unction ............................................................................................................................... 24 8.7. 10b ase -t r eceive f unction ............................................................................................................................... ...24 8.8. a uto -n egotiation for utp ............................................................................................................................ ......24 8.9. c rossover d etection and a uto c orrection .....................................................................................................25 8.10. p olarity c orrection ............................................................................................................................... ..............25 9. general function description................................................................................................... ...................26 9.1. r eset ............................................................................................................................... .........................................26 9.1.1. hardware reset ....................................................................................................................................................26 9.1.2. software reset ................................................................................................................. .....................................26 9.2. ieee 802.3 x f ull d uplex f low c ontrol ............................................................................................................27 9.3. h alf d uplex f low c ontrol ............................................................................................................................... ..27 9.3.1. back-pressu re mode ............................................................................................................. ...............................27 9.4. s earch and l earning ............................................................................................................................... .............28 9.5. svl and ivl/svl ...................................................................................................................................................28 9.6. i llegal f rame f iltering ............................................................................................................................... ........28 9.7. ieee 802.3 r eserved g roup a ddresses f iltering c ontrol .............................................................................29 9.8. b roadcast /m ulticast /u nknown da s torm c ontrol .....................................................................................30
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller iv track id: jatr-2265-11 rev. 1.0 9.9. p ort s ecurity f unction ............................................................................................................................... .........30 9.10. mib c ounters ............................................................................................................................... ..........................30 9.11. p ort m irroring ............................................................................................................................... .......................30 9.12. vlan f unction ............................................................................................................................... .......................31 9.12.1. port-based vlan ................................................................................................................ ............................31 9.12.2. ieee 802.1q ta g-based vlan..................................................................................................... ..................31 9.12.3. protocol-based vlan ............................................................................................................ .........................32 9.12.4. port vid ..........................................................................................................................................................32 9.13. q o s f unction ............................................................................................................................... ...........................33 9.13.1. input bandwidt h control ........................................................................................................ .........................33 9.13.2. priority a ssignment ............................................................................................................ .............................33 9.13.3. priority queu e scheduling...................................................................................................... .........................33 9.13.4. ieee 802.1p/q and dscp remarking ............................................................................................... .............34 9.13.5. acl-based priority ............................................................................................................. ............................34 9.14. igmp & mld s nooping f unction .........................................................................................................................35 9.15. ieee 802.1 x f unction ............................................................................................................................... ..............35 9.15.1. port-based ac cess cont rol..............................................................................................................................35 9.15.2. authorized port-based access control ........................................................................................... ................35 9.15.3. port-based access co ntrol direction............................................................................................ ..................35 9.15.4. mac-based acce ss cont rol.............................................................................................................................35 9.15.5. mac-based access co ntrol direction ............................................................................................. ...............36 9.15.6. optional unauthor ized behavior................................................................................................. ....................36 9.15.7. guest vlan ..................................................................................................................... ................................36 9.16. ieee 802.1d f unction ............................................................................................................................... .............36 9.17. e mbedded 8051........................................................................................................................................................37 9.18. r ealtek c able t est (rtct) ......................................................................................................................... ........37 9.19. led i ndicators ............................................................................................................................... ........................37 9.20. g reen e thernet ............................................................................................................................... .......................39 9.20.1. link-on and cable le ngth powe r saving .......................................................................................... .............39 9.20.2. link-down po wer sa ving ......................................................................................................... .......................39 9.21. ieee 802.3 az e nergy e fficient e thernet (eee) f unction ...............................................................................39 9.22. i nterrupt p in for e xternal cpu .........................................................................................................................39 10. interface de scriptions ......................................................................................................... ........................40 10.1. eeprom smi h ost to eeprom ......................................................................................................................... ..40 10.2. eeprom smi s lave for e xternal cpu..............................................................................................................41 10.3. spi s lave for e xternal cpu............................................................................................................................ ....42 10.3.1. spi-slave interfa ce access format .............................................................................................. ...................42 10.4. g eneral p urpose i nterface ............................................................................................................................... ...43 10.4.1. extension ports gmii mo de interface (1gbps).................................................................................... ...........44 10.4.2. extension ports rgmii mode (1gbps)............................................................................................. ...............46 10.4.3. extension ports mii mac/phy mo de interface (10/100mbps) ......................................................................47 11. register descriptions .......................................................................................................... ..........................49 11.1. pcs r egister (phy 1, 2) ............................................................................................................................. ............49 11.2. r egister 0: c ontrol ............................................................................................................................... ................50 11.3. r egister 1: s tatus ............................................................................................................................... ...................51 11.4. r egister 2: phy i dentifier 1 .............................................................................................................................. ...52 11.5. r egister 3: phy i dentifier 2 .............................................................................................................................. ...52 11.6. r egister 4: a uto -n egotiation a dvertisement .................................................................................................52 11.7. r egister 5: a uto -n egotiation l ink p artner a bility .......................................................................................53 11.8. r egister 6: a uto -n egotiation e xpansion ..........................................................................................................54 11.9. r egister 7: a uto -n egotiation p age t ransmit r egister ..................................................................................54 11.10. r egister 8: a uto -n egotiation l ink p artner n ext p age r egister ............................................................54 11.11. r egister 9: 1000b ase -t c ontrol r egister ....................................................................................................55
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller v track id: jatr-2265-11 rev. 1.0 11.12. r egister 10: 1000b ase -t s tatus r egister .....................................................................................................55 11.13. r egister 15: e xtended s tatus .........................................................................................................................56 12. electrical cha racteristics..................................................................................................... .................57 12.1. a bsolute m aximum r atings ............................................................................................................................... .57 12.2. r ecommended o perating r ange ..........................................................................................................................57 12.3. t hermal c haracteristics ............................................................................................................................... ......58 12.3.1. assembly de scription ........................................................................................................... ...........................58 12.3.2. material pr opertie s ............................................................................................................ .............................58 12.3.3. simulation conditions .......................................................................................................... ...........................58 12.3.4. thermal performance of lqfp-128 on pcb under still ai r convection.......................................................58 12.3.5. thermal performance of lqfp-128 on pcb under forced convection........................................................59 12.4. dc c haracteristics ............................................................................................................................... ................59 12.5. ac c haracteristics ............................................................................................................................... ................60 12.5.1. eeprom smi host mode timi ng characteristics .................................................................................... .....60 12.5.2. eeprom smi slave mode timi ng characteristics ................................................................................... .....61 12.5.3. spi slave mode timing characteristics .......................................................................................... ................62 12.5.4. mdio slave mode timi ng characte ristics ......................................................................................... ............63 12.5.5. gmii timing c haracteristics.................................................................................................... .......................64 12.5.6. mii mac mode timing ............................................................................................................ .......................65 12.5.7. mii phy mode timing ............................................................................................................ ........................66 12.5.8. rgmii timing char acteristics ................................................................................................... .....................67 12.6. p ower and r eset c haracteristics ......................................................................................................................69 13. mechanical dimensions.................................................................................................................................70 14. ordering information ........................................................................................................... ........................71
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller vi track id: jatr-2265-11 rev. 1.0 list of tables t able 1. p in a ssignment t able ............................................................................................................................... .................8 t able 2. m edia d ependent i nterface p ins ...........................................................................................................................11 t able 3. e xtension gmac0 gmii p ins ............................................................................................................................... ...12 t able 4. e xtension gmac1 gmii p ins ............................................................................................................................... ...13 t able 5. e xtension gmac0 rgmii p ins ............................................................................................................................... 14 t able 6. e xtension gmac1 rgmii p ins ............................................................................................................................... 15 t able 7. e xtension gmac0 mii p ins (mii mac m ode or mii phy m ode ).......................................................................16 t able 8. e xtension gmac1 mii p ins (mii mac m ode or mii phy m ode ).......................................................................17 t able 9. led p ins ............................................................................................................................... ......................................19 t able 10. c onfiguration s trapping p ins ............................................................................................................................... 20 t able 11. c onfiguration s trapping p ins (disautoload and dis_8051) ......................................................................21 t able 12. m anagement i nterface p ins ............................................................................................................................... ...21 t able 13. m iscellaneous p ins ............................................................................................................................... ..................22 t able 14. t est p ins ............................................................................................................................... .....................................22 t able 15. p ower and gnd p ins ............................................................................................................................... .................22 t able 16. m edia d ependent i nterface p in m apping .............................................................................................................25 t able 17. r eserved m ulticast a ddress c onfiguration t able .........................................................................................29 t able 18. led d efinitions ............................................................................................................................... .........................37 t able 19. RTL8363SB e xtension p ort 0 p in d efinitions .....................................................................................................43 t able 20. RTL8363SB e xtension p ort 1 p in d efinitions .....................................................................................................44 t able 21. e xtension gmac0 gmii m ode p ins .......................................................................................................................44 t able 22. e xtension gmac1 gmii m ode p ins .......................................................................................................................45 t able 23. e xtension gmac0 rgmii p ins ............................................................................................................................... 46 t able 24. e xtension gmac1 rgmii p ins ............................................................................................................................... 46 t able 25. e xtension gmac0 mii p ins ............................................................................................................................... .....47 t able 26. e xtension gmac1 mii p ins ............................................................................................................................... .....47 t able 27. pcs r egister (phy 1, 2)............................................................................................................................. ..............49 t able 28. r egister 0: c ontrol ............................................................................................................................... .................50 t able 29. r egister 1: s tatus ............................................................................................................................... .....................51 t able 30. r egister 2: phy i dentifier 1.............................................................................................................................. .....52 t able 31. r egister 3: phy i dentifier 2.............................................................................................................................. .....52 t able 32. r egister 4: a uto -n egotiation a dvertisement ...................................................................................................52 t able 33. r egister 5: a uto -n egotiation l ink p artner a bility ........................................................................................53 t able 34. r egister 6: a uto -n egotiation e xpansion ............................................................................................................54 t able 35. r egister 7: a uto -n egotiation p age t ransmit r egister ....................................................................................54 t able 36. r egister 8: a uto -n egotiation l ink p artner n ext p age r egister ...................................................................54 t able 37. r egister 9: 1000b ase -t c ontrol r egister ...........................................................................................................55 t able 38. r egister 10: 1000b ase -t s tatus r egister ............................................................................................................55 t able 39. r egister 15: e xtended s tatus ............................................................................................................................... 56 t able 40. a bsolute m aximum r atings ............................................................................................................................... ...57 t able 41. r ecommended o perating r ange ...........................................................................................................................57 t able 42. a ssembly d escription ............................................................................................................................... ..............58 t able 43. m aterial p roperties ............................................................................................................................... ................58 t able 44. s imulation c onditions ............................................................................................................................... ............58 t able 45. t hermal p erformance of lqfp-128 on pcb u nder s till a ir c onvection .....................................................58 t able 46. t hermal p erformance of lqfp-128 on pcb u nder f orced c onvection ........................................................59 t able 47. dc c haracteristics ............................................................................................................................... ..................59 t able 48. eeprom smi h ost m ode t iming c haracteristics .............................................................................................61 t able 49. eeprom smi s lave m ode t iming c haracteristics ...........................................................................................61 t able 50. spi-s lave m ode t iming c haracteristics .............................................................................................................62 t able 51. mdio t iming c haracteristics and r equirement ...............................................................................................63 t able 52. gmii t iming c haracteristics ............................................................................................................................... .64
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller vii track id: jatr-2265-11 rev. 1.0 t able 53. mii mac m ode t iming ............................................................................................................................... ..............65 t able 54. mii phy m ode t iming c haracteristics ................................................................................................................66 t able 55. rgmii t iming c haracteristics ..............................................................................................................................6 8 t able 56. p ower and r eset c haracteristics ........................................................................................................................69 t able 57. o rdering i nformation ............................................................................................................................... .............71 list of figures f igure 1. 2-p ort 1000b ase -t r outer with d ual mii/rgmii/gmii .....................................................................................5 f igure 2. b lock d iagram ............................................................................................................................... ...........................6 f igure 3. p in a ssignments (lqfp-128) ..................................................................................................................... ...............7 f igure 4. c onceptual e xample of p olarity c orrection ..................................................................................................25 f igure 5. p rotocol -b ased vlan f rame f ormat and f low c hart ..................................................................................32 f igure 6. max-min s cheduling d iagram ...........................................................................................................................34 f igure 7. p ull -u p and p ull -d own of led p ins for s ingle -c olor led...........................................................................38 f igure 8. p ull -u p and p ull -d own of led p ins for b i -c olor led...................................................................................38 f igure 9. smi s tart and s top c ommand ..............................................................................................................................4 0 f igure 10. eeprom smi h ost to eeprom......................................................................................................................... ...40 f igure 11. eeprom smi h ost m ode f rame ...........................................................................................................................40 f igure 12. eeprom smi w rite c ommand for s lave m ode ................................................................................................41 f igure 13. eeprom smi r ead c ommand for s lave m ode ..................................................................................................41 f igure 14. spi-s lave w rite c ommand a ccess f ormat ........................................................................................................42 f igure 15. spi-s lave r ead c ommand a ccess f ormat .........................................................................................................42 f igure 16. mac gmii m ode i nterface (1g bps ) s ignal d iagram ........................................................................................45 f igure 17. rgmii m ode i nterface s ignal d iagram .............................................................................................................46 f igure 18. mii phy m ode i nterface (100m bps ) s ignal d iagram .......................................................................................48 f igure 19. mii mac m ode i nterface (100m bps ) s ignal d iagram ......................................................................................48 f igure 20. eeprom smi h ost m ode t iming c haracteristics ............................................................................................60 f igure 21. sck/sda p ower on t iming ............................................................................................................................... .....60 f igure 22. eeprom a uto -l oad t iming ............................................................................................................................... ...60 f igure 23. eeprom smi s lave m ode t iming c haracteristics ..........................................................................................61 f igure 24. spi-s lave m ode t iming c haracteristics ............................................................................................................62 f igure 25. mdio s ourced by the m aster ..............................................................................................................................6 3 f igure 26. mdio s ourced by the RTL8363SB (s lave ) .........................................................................................................63 f igure 27. gmii t iming c haracteristics ............................................................................................................................... 64 f igure 28. mii mac m ode c lock to d ata o utput d elay t iming ......................................................................................65 f igure 29. mii mac m ode i nput t iming ............................................................................................................................... ..65 f igure 30. mii phy m ode o utput t iming ............................................................................................................................... 66 f igure 31. mii phy m ode c lock o utput to d ata i nput d elay t iming .............................................................................66 f igure 32. rgmii o utput t iming c haracteristics (rg x _txclk_delay=0) ................................................................67 f igure 33. rgmii o utput t iming c haracteristics (rg x _txclk_delay=2 ns ) ............................................................67 f igure 34. rgmii i nput t iming c haracteristics (rg x _rxclk_delay=0)....................................................................67 f igure 35. rgmii i nput t iming c haracteristics (rg x _rxclk_delay=2 ns )................................................................68 f igure 36. p ower and r eset c haracteristics .......................................................................................................................69
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 1 track id: jatr-2265-11 rev. 1.0 1. general description the RTL8363SB-cg is an lqfp128, high-performance 2+2-port 10/100/1000m ethernet switch. it features low-power integrated dual-port gigabit phys that support 1000base-t, 100base-tx, and 10base-t. for specific applications, the RTL8363SB supports tw o extra interfaces that can be configured as gmii/rgmii/mii interfaces. the rtl8363s b integrates all the functions of a high-speed switch system; including sram for packet buffering, non-blocking switch fabric, and internal register management into a single cmos device. only a 25mhz crystal is required; an optiona l eeprom is offered for internal register configuration. the embedded packet storage sram in the r tl8363sb features superior memory management technology to efficiently utilize memory space. the RTL8363SB integrates a 2k-entry look-up table with a 4-way xor hashing algorithm for address searching and learning. the table provides read/write access from the eeprom serial management interface (s mi), media independent interface management (miim), or spi interface. each of the entries can be configured as a static entry. normal entry aging time is between 200 and 400 seconds. eight filtering da tabases are used to provide independent vlan learning and shared vlan learning (ivl/svl) functions. the extension gmac0 and extension gmac1 of the RTL8363SB implement dual gmii/rgmii/mii interfaces. these interfaces c ould be connected to an external phy, mac, cpu, or risc for specific applications. in router applicati ons, the RTL8363SB supports port vid (p vid) for each port to insert a pvid in the vlan tag on egress. when using this function, vid information carried in the vlan tag will be changed to pvid. note: the RTL8363SB extra interface (extensi on gmac0 and extension gmac1) supports: dual-port gigabit media independent interface (gmii) dual-port reduced gigabit media independent interface (rgmii) dual-port media indepe ndent interface (mii) the RTL8363SB supports standard 802.3x flow control frames for full d uplex, and optional backpressure for half duplex. it determines when to invoke the flow control mechanism by checking the availability of system resources, including the packet buffers and transmitting queues. the RTL8363SB supports broadcast/multicast output dropping, and will forward broadcast/multicast packets to non-blocked ports only. for ip multicast applicati ons, the RTL8363SB supports ipv4 igmpv1/v2/v3 and ipv6 mldv1/v2 snooping. in order to support flexible traffic classificati on, the RTL8363SB supports 64-entry acl rule check and multiple actions options. each port can optionally enable or disable the acl rule check function. the acl rule key can be based on packet physical port, layer2, layer3, and layer4 information. when an acl rule matches, the action taken is configurable to drop/permit/redirect/mirror, change priority value in 802.1q/q tag, and rate policing. the rate policing m echanism supports from 8kbps to 1gbps (in 8kbps steps). in bridge operation the RTL8363SB s upports 16 sets of port configurat ions: disable, block, learning, and forwarding for spanning tree protocol and multiple spanning tree protocol. to meet security and management application requirements, the RTL8363SB supports ieee 802.1x port-based/mac-based access control. for those ports that do not pa ss ieee 802.1x authentication, the RTL8363SB provides a
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 2 track id: jatr-2265-11 rev. 1.0 port-based/mac-based guest vlan function for them to access limited network resources. a 1-set port mirroring function is configured to mirror traffic (rx, tx, or both) appearing on one of the switch?s ports. support is provided on each port for multiple rfc mib counters, for easy debug and diagnostics. to improve real-time and multimedia networking a pplications, the RTL8363SB supports eight priority assignments for each received packet. these are ba sed on (1) port-based priority; (2) 802.1p/q vlan tag priority; (3) dscp field in ipv4/ipv6 header; and (4) acl-assigned priority. each out put port supports a weighted ratio of eight priority qu eues to fit bandwidth requirements in different applications. the input bandwidth control function helps lim it per-port traffic utilization. ther e is one leaky bucket for average packet rate control for each queue of all ports. queue scheduling algo rithm can use strict priority (sp) or weighted fair queue (wfq) or mixed. the RTL8363SB provides a 4k-entry vlan table fo r 802.1q port-based, tag-based, and protocol-based vlan operation to separate logica l connectivity from physical connectivity. the RTL8363SB supports four protocol-based vlan configur ations that can optionally select ethertype, llc, and rfc1042 as the search key. each port may be set to any to pology via eeprom upon rese t, or eeprom smi slave after reset. in router applications, the router may want to know the input port of the incoming packet. the RTL8363SB supports an option to insert a vlan ta g with vid=port vid (pvid) on each egress port. the RTL8363SB also provides an option to admit vl an tagged packets with a specific pvid only. if this function is enabled, the RTL8363SB will drop al l non-tagged packets and packets with an incorrect pvid.
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 3 track id: jatr-2265-11 rev. 1.0 2. features ? single-chip 2+2-port gigabit non-blocking switch architecture ? embedded dual-port 10/100/1000base-t phy ? each port supports full duplex 10/100/1000m connectivity (half duplex only supported in 10/100m mode) ? extra interface (extension gmac0 and extension gmac1) supports ? dual-port media independent interface (mii) ? dual-port reduced gigabit media independent interface (rgmii) ? dual-port gigabit media independent interface (gmii) ? full-duplex and half- duplex operation with ieee 802.3x flow control and backpressure ? supports 9216-byte jumbo packet length forwarding at wire speed ? supports realtek cable test (rtct) ? supports 64-entry acl rules ? search keys support physical port, layer2, layer3, and layer4 information ? actions include mirror, redirect, dropping, priority adjustment, traffic policing, cvlan decision, and svlan assignment gpio control, interrupt and logging counter ? supports 5 types of user defined acl rule format for 64 acl rules ? optional per-port enable/disable of acl function ? optional setting of per-port action to take when acl mismatch ? supports ieee 802.1q vlan ? supports 4k vlans and 32 extra enhanced vlans ? supports un-tag definition in each vlan ? supports vlan policing and vlan forwarding decision ? port-based, tag-based, and protocol- based vlan ? up to 4 protocol-based vlan entries ? per-port and per-vlan egress vlan tagging and un-tagging ? supports ivl, svl, and ivl/svl ? supports 2k-entry mac address table with 4-way hash algorithm ? up to 2k l2/l3 filtering database ? per-port mac learning limitation ? supports spanning tree port behavior configuration ? ieee 802.1w rapid spanning tree ? ieee 802.1s multiple spanning tree with up to 16 spanning tree instances ? supports ieee 802.1x access control protocol ? port-based access control ? mac-based access control ? guest vlan ? supports auto denial-of-service protection ? supports h/w igmp/mld snooping ? igmpv1/v2/3 and mld v1/v2 ? supports fast leave
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 4 track id: jatr-2265-11 rev. 1.0 ? static router port configuration ? dynamic router port learning and aging ? supports quality of service (qos) ? supports per-port input bandwidth control ? traffic classification based on ieee 802.1p/q priority definition, physical port, ip dscp field, acl definition, vlan based priority, mac based priority and svlan based priority ? eight priority queues per port ? per queue flow control ? min-max scheduling ? strict priority and weighted fair queue (wfq) to provide minimum bandwidth ? one leaky bucket to constrain the average packet rate of each queue ? supports rate limiting (64 shared meters, with 8kpbs granulation) ? rfc mib counter ? mib-ii (rfc 1213) ? ethernet-like mib (rfc 3635) ? interface group mib (rfc 2863) ? rmon (rfc 2819) ? bridge mib (rfc 1493) ? bridge mib extension (rfc 2674) ? supports stacking vlan and port isolation with 8 enhanced filtering databases ? supports ieee 802.1ad stacking vlan ? supports 64 svlans ? supports 32 l2/ipv4 multicast mappings to svlan ? supports mac-based 1:n vlan ? supports 2 ieee 802.3ad link aggregation port groups ? supports port mirror f unction for one source port to multiple destination ports ? supports oam and eee lldp (energy efficient ethernet link layer discovery protocol) ? supports loop detection ? security filtering ? disable learning for each port ? disable learning-table aging for each port ? drop unknown da for each port ? broadcast/multicast/unknown da storm control protects system from attack by hackers ? supports realtek green ethernet ? link-on cable length power saving ? link-down power saving ? supports 1 interrupt output to external cpu for notification ? each port supports 3 led outputs ? management interface supports ? eeprom smi slave interface ? media independent interface management (miim) ? spi slave interface ? supports 32k-byte eeprom space for configuration ? integrated 8051 microprocessor. ? 25mhz crystal or 3.3v osc input ? lqfp 128-pin package
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 5 track id: jatr-2265-11 rev. 1.0 3. system applications ? 2-port 1000base-t router with dual mii/rgmii/gmii interfaces 4. application examples 4.1. 2-port 1000base-t router with dual mii/rgmii/gmii figure 1. 2-port 1000base-t router with dual mii/rgmii/gmii note: extra interface (extension gmac0 and extension gmac1) in mii/rgmii/gmii mode.
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 6 track id: jatr-2265-11 rev. 1.0 5. block diagram p1 gmac p2 gmac packet buffer sram 2k mac address table linking lists sram controller queue management lookup engine control registers + mib counter 4096 vlan table pll sck/sda management interface i 2 c host giga-phy pcs utp giga-phy pcs utp extension interface 0 mii/gmii/ rgmii extension gmac 0 extension gmac 1 extension interface 1 25mhz crystal 8051 gnic mii/gmii/ rgmii gnic mac mmd_mdc/mdio spis figure 2. block diagram
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 7 track id: jatr-2265-11 rev. 1.0 6. pin assignments 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 e0_doclk / g0_txclk lqfp 128 package size 14mm x 14mm 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 p2mdicn p2mdidp agnd mdiref avddh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 avddl gnd avddh avddl rtt1 gnd rtt2 gnd dvddl interrupt reserved e0_do1 g0_txd1 / rg0_txd1 / m0m_txd1 / m0p_rxd1 e0_do0 / g0_txd0 / rg0_txd0 / m0m_txd0 / m0p_rxd0 gnd gnd gnd avddh reserved pllvddl0 p1mdidn p2mdicp reserved reserved e1_crs / g1_crs / m1m_crs e1_do7 / g1_txd7 e1_do6 / g1_txd6 e1_do5 / g1_txd5 e1_do2 / g1_txd2 / rg1_txd2 / m1m_txd2 / m1p_rxd2 e1_do1 / g1_txd1 / rg1_txd1 / m1m_txd1 / m1p_rxd1 e1_do0 / g1_txd0 / rg1_txd0 / m1m_txd0 / m1p_rxd0 e1_goclk / g1_gtxc / rg1_txclk / m1m_txclk / m1p_rxclk e1_doclk / g1_txclk gnd e1_diclk / g1_rxclk / rg1_rxclk / m1m_rxclk / m1p_txclk e1_didv / g1_rxdv / rg1_rxctl / m1m_rxdv / m1p_txen e1_di0 / g1_rxd0 / rg1_rxd0 / m1m_rxd0 / m1p_txd0 e1_di1 / g1_rxd1 / rg1_rxd1 / m1m_rxd1 / m1p_txd1 e1_di2 / g1_rxd2 / rg1_rxd2 / m1m_rxd2 / m1p_txd2 e1_di3 / g1_rxd3 / rg1_rxd3 / m1m_rxd3 / m1p_txd3 e1_di4 / g1_rxd4 e1_di5 / g1_rxd5 e1_di7 / g1_rxd7 dvddio_1 dvddio_0 e0_di7 / g0_rxd7 e0_di6 / g0_rxd6 e0_di5 / g0_rxd5 e0_di4 / g0_rxd4 e0_di2 / g0_rxd2 / rg0_rxd2 / m0m_rxd2 / m0p_txd2 p2led0 / disautoload p2led1 p1led1 smi_sel sck / spis_ck gnd sda / spis_di spis_csi p1mdibp p1mdibn gnd p1mdicp avddh p2mdiap p2mdibp gnd e1_doen / g1_txen / rg1_txctl / m1m_txen / m1p_rxdv e0_didv / g0_rxdv / rg0_rxctl / m0m_rxdv / m0p_txen e0_di0 / g0_rxd0 / rg0_rxd0 / m0m_rxd0 / m0p_txd0 e0_di1 / g0_rxd1 / rg0_rxd1 / m0m_rxd1 / m0p_txd1 e0_diclk / g0_rxclk / rg0_rxclk / m0m_rxclk / m0p_txclk e0_do2 / g0_txd2 / rg0_txd2 / m0m_txd2 / m0p_rxd2 e0_do3 / g0_txd3 / rg0_txd3 / m0m_txd3 / m0p_rxd3 e0_do6 / g0_txd6 avddh e0_di3 / g0_rxd3 / rg0_rxd3 / m0m_rxd3 / m0p_txd3 e0_do5 / g0_txd5 e0_goclk / g0_gtxc / rg0_txclk / m0m_txclk / m0p_rxclk e1_di6 / g1_rxd6 e0_crs / g0_crs / m0m_crs e0_doen / g0_txen / rg0_txctl / m0m_txen / m0p_rxdv e0_do4 / g0_txd4 reserved e1_do3 / g1_txd3 / rg1_txd3 / m1m_txd3 / m1p_rxd3 dvddio_1 p2mdidn avddh reserved avddl p2led2 / dis_8051 xtali gnd p1mdiap p1mdidp p2mdibp dvddio avddh gnd gnd xtalo nreset p1mdian p1mdicn p2mdian avddh p1led2 / reserved p1led0 / reserved spis_do avddl pllgnd0 gnd avddl avddl dvddl dis_spis dvddl dvddio_0 e0_do7 / g0_txd7 gnd gnd avddl avddh e1_do4 / g1_txd4 figure 3. pin assignments (lqfp-128) 6.1. package identification green package is indicated by the ?g? in gxxxx (figure 3).
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 8 track id: jatr-2265-11 rev. 1.0 6.2. pin assignments table upon reset: defined as a short time af ter the end of a hardware reset. after reset: defined as the time afte r the specified ?upon reset? time. i: input pin ai: analog input pin o: output pin ao: analog output pin i/o: bi-directional input/output pin ai/o : analog bi-directional input/output pin p: digital power pin ap: analog power pin g: digital ground pin ag: analog ground pin i pu : input pin with pull-up resistor; (typical value = 75k ohm) o pu : output pin with pull-up resistor; (typical value = 75k ohm) i s : input pin with schmitt trigger table 1. pin assignment table name pin no. type p2mdicp 1 ai/o p2mdicn 2 ai/o p2mdidp 3 ai/o p2mdidn 4 ai/o avddh 5 ap av d d l 6 a p gnd 7 g avddh 8 ap agnd 9 ag mdiref 10 ao av d d l 11 a p rtt1 12 ao gnd 13 g rtt2 14 ao avddh 15 ap dvddio 16 p gnd 17 g interrupt 18 o pu dvddl 19 p reserved 20 i reserved 21 i avddh 22 ap name pin no. type gnd 23 g gnd 24 g gnd 25 g gnd 26 g avddl 27 ap avddh 28 ap avddl 29 ap avddh 30 ap reserved 31 ao reserved 32 ao gnd 33 g gnd 34 g reserved 35 i e1_crs/g1_crs/m1m _crs 36 i e1_do7/g1_txd7 37 o e1_do6/g1_txd6 38 o e1_do5/g1_txd5 39 o e1_do4/g1_txd4 40 o e1_do3/g1_txd3/rg1_txd3/ m1m_txd3/m1p_rxd3 41 o e1_do2/g1_txd2/rg1_txd2/ m1m_txd2/m1p_rxd2 42 o
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 9 track id: jatr-2265-11 rev. 1.0 name pin no. type e1_do1/g1_txd1/rg1_txd1/ m1m_txd1/m1p_rxd1 43 o e1_do0/g1_txd0/rg1_txd0/ m1m_txd0/m1p_rxd0 44 o e1_doen/g1_txen/ rg1_txctl/m1m_txen/ m1p_rxdv 45 o dvddio_1 46 p e1_goclk/g1_gtxc/ rg1_txclk/m1m_txclk/ m1p_rxclk 47 i/o e1_doclk /g1_txclk 48 i gnd 49 g e1_diclk/g1_rxclk/ rg1_rxclk/m1m_rxclk/ m1p_txclk 50 i/o e1_didv/g1_rxdv/ rg1_rxctl/m1m_rxdv/ m1p_txen 51 i e1_di0/g1_rxd0/rg1_rxd0/ m1m_rxd0/m1p_txd0 52 i e1_di1/g1_rxd1/rg1_rxd1/ m1m_rxd1/m1p_txd1 53 i e1_di2/g1_rxd2/rg1_rxd2/ m1m_rxd2/m1p_txd2 54 i e1_di3/g1_rxd3/rg1_rxd3/ m1m_rxd3/m1p_txd3 55 i e1_di4/g1_rxd4 56 i e1_di5/g1_rxd5 57 i e1_di6/g1_rxd6 58 i e1_di7/g1_rxd7 59 i dvddio_1 60 p dvddio_0 61 p dvddl 62 p e0_crs/g0_crs/m0m_crs 63 i e0_di7/g0_rxd7 64 i e0_di6/g0_rxd6 65 i e0_di5/g0_rxd5 66 i e0_di4/g0_rxd4 67 i e0_di3/g0_rxd3/rg0_rxd3/ m0m_rxd3/m0p_txd3 68 i e0_di2/g0_rxd2/rg0_rxd2/ m0m_rxd2/m0p_txd2 69 i e0_di1/g0_rxd1/rg0_rxd1/ m0m_rxd1/m0p_txd1 70 i e0_di0/g0_rxd0/rg0_rxd0/ m0m_rxd0/m0p_txd0 71 i name pin no. type e0_didv/g0_rxdv/ rg0_rxctl/m0m_rxdv/ m0p_txen 72 i e0_diclk/g0_rxclk/ rg0_rxclk/m0m_rxclk/ m0p_txclk 73 i/o e0_doclk/g0_txclk 74 i e0_goclk/g0_gtxc/ rg0_txclk/m0m_txclk/ m0p_rxclk 75 i/o e0_doen/g0_txen/ rg0_txctl/m0m_txen/ m0p_rxdv 76 o e0_do0/g0_txd0/rg0_txd0/ m0m_txd0/m0p_rxd0 77 o e0_do1/g0_txd1/rg0_txd1/ m0m_txd1/m0p_rxd1 78 o e0_do2/g0_txd2/rg0_txd2/ m0m_txd2/m0p_rxd2 79 o e0_do3/g0_txd3/rg0_txd3/ m0m_txd3/m0p_rxd3 80 o e0_do4/g0_txd4 81 o e0_do5/g0_txd5 82 o e0_do6/g0_txd6 83 o e0_do7/g0_txd7 84 o dvddio_0 85 p dvddl 86 p dis_spis 87 i/o pu reserved 88 i/o pu p2led2/dis_8051 89 i/o pu gnd 90 g p2led0/disautoload 91 i/o pu p2led1/gpio12 92 i/o pu p1led2/reserved 93 i/o pu p1led0/reserved 94 i/o pu p1led1 95 i/o pu led_ck/smi_sel 96 i/o pu xtalo 97 ao xtali 98 ai spis_ck/sck/mmd_mdc 99 i/o pu gnd 100 g spis_do 101 o spis_di /sda/mmd_mdio 102 i/o pu spis_csi 103 i nreset 104 i s gnd 105 g
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 10 track id: jatr-2265-11 rev. 1.0 name pin no. type avddh 106 ap avddl 107 ap avddh 108 ap p1mdiap 109 ai/o p1mdian 110 ai/o p1mdibp 111 ai/o p1mdibn 112 ai/o avddl 113 ap gnd 114 g p1mdicp 115 ai/o p1mdicn 116 ai/o p1mdidp 117 ai/o name pin no. type p1mdidn 118 ai/o pllvddl0 119 ap pllgnd0 120 ag gnd 121 g avddh 122 ap p2mdiap 123 ai/o p2mdian 124 ai/o p2mdibp 125 ai/o p2mdibn 126 ai/o gnd 127 g avddl 128 ap
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 11 track id: jatr-2265-11 rev. 1.0 7. pin descriptions 7.1. media dependent interface pins table 2. media dependent interface pins pin name pin no. type drive (ma) description p1mdiap/n p1mdibp/n p1mdicp/n p1mdidp/n 109 110 111 112 115 116 117 118 ai/o 10 port 1 media dependent interface a~d. for 1000base-t operation, differential data from the media is transmitted and received on all four pairs. fo r 100base-tx and 10base-t operation, only mdiap/n and mdibp/n are used. auto mdix can reverse the pairs mdiap/n and mdibp/n. each of the differential pairs has an internal 100-ohm termination resistor. p2mdiap/n p2mdibp/n p2mdicp/n p2mdidp/n 123 124 125 126 1 2 3 4 ai/o 10 port 2 media dependent interface a~d. for 1000base-t operation, differential data from the media is transmitted and received on all four pairs. fo r 100base-tx and 10base-t operation, only mdiap/n and mdibp/n are used. auto mdix can reverse the pairs mdiap/n and mdibp/n. each of the differential pairs has an internal 100-ohm termination resistor. 7.2. general purpose interfaces the RTL8363SB supports multi-function general purpose interfaces that can be configured as mii/rgmii/gmii mode for exte nsion gmac interfaces. the r tl8363sb supports two extension interfaces (extension gmac0 and extension gmac1) fo r connecting with an external phy, mac, or cpu in specific applications. these extension inte rfaces support gmii, rgmii, mii mac mode, or mii phy mode via regist er configuration. 7.2.1. gmii interface pins the extension gmac0 and extension gmac1 of the RTL8363SB support two gmii interfaces when register configuration is set to gm ii mode interface. when the extension interface operates at 1gbps, the interface will be gmii. when the extension interf aces operate at 100mbps/10mbps, the interface will be mii. note that 1gbps half duplex is not supported in this configuration.
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 12 track id: jatr-2265-11 rev. 1.0 table 3. extension gmac0 gmii pins pin name pin no. type drive (ma) description g0_crs 63 i - g0_crs carrier sense input when the extension gmac0 gmii interface operates in 10/100 mii half duplex mode. g0_crs is only valid in 10/100mbps mii half duplex mode. it is asserted high when a valid carrier is detected on the media. this pin must be pulled low with a 1k ohm resistor when not used. g0_rxd7 g0_rxd6 g0_rxd5 g0_rxd4 g0_rxd3 g0_rxd2 g0_rxd1 g0_rxd0 64 65 66 67 68 69 70 71 i - g0_rxd[7:0] extension gmac0 gmii receive data input. received data is received synchron ously at the rising edge of g0_rxclk. in 10/100mbps mii mode, only g0_rxd[3:0] are available. these pins must be pulled low with a 1k ohm resistor when not used. g0_rxdv 72 i - g0_rxdv ex tension gmac0 gmii recei ve data valid input. receive data valid is received synchronously at the rising edge of g0_rxclk in both 1gbps gmii and 10/100mbps mii mac mode. this pin must be pulled low with a 1k ohm resistor when not used. g0_rxclk 73 i - g0_rxclk extension gmac0 gmii receive clock input. in gmii mode: 125mhz receive clock. used to synchronize g0_rxd[7:0] and g0_rxdv. in mii 10/100mbps mode: g0_rxclk is 2.5/25mhz. used to synchronize g0_rxd[3:0], g0_rxdv, and g0_crs. this pin must be pulled low with a 1k ohm resistor when not used. g0_txclk 74 i - g0_txclk 2.5/25mhz transmit clock input when the extension gmac0 gmii interface operates in 10/100 mii mode. 2.5/25mhz clock driven by phy when operating in 10/100mbps mii mode. used to synchronize g0_tx[3:0] and g0_txen. this pin must be pulled low with a 1k ohm resistor when not used. g0_gtxc 75 o - g0_gtxc extension gmac0 gmii transmit clock output. 125mhz transmit clock output when gmii is operating at 1gbps. used to synchronize g0_txd[7:0] and g0_txen. g0_txen 76 o - g0_txen extension gmac0 gmii transmit data enable output. transmit enable that is sent sync hronously at the rising edge of g0_gtxc in gmii mode. transmit enable that is sent sync hronously at the rising edge of g0_txclk in 10/100mbps mii mode. g0_txd0 g0_txd1 g0_txd2 g0_txd3 g0_txd4 g0_txd5 g0_txd6 g0_txd7 77 78 79 80 81 82 83 84 o - g0_txd [7:0] extension gmac0 gmii transmit data output. in 1000mbps gmii mode, g0_txd [7:0] transmitted data is sent synchronously at the rising edge of g0_gtxc. in 10/100mbps mii mode, only g0_txclk [3:0] are available for transmitting and receiving data at the rising edge of g0_txclk.
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 13 track id: jatr-2265-11 rev. 1.0 table 4. extension gmac1 gmii pins pin name pin no. type drive (ma) description g1_crs 36 i - g1_crs carrier sense input when the extension gmac1 gmii interface operates in 10/100 mii half duplex mode. g1_crs is only valid in 10/100mbps mii half duplex mode. it is asserted high when a valid carrier is detected on the media. this pin must be pulled low with a 1k ohm resistor when not used. g1_txd7 g1_txd6 g1_txd5 g1_txd4 g1_txd3 g1_txd2 g1_txd1 g1_txd0 37 38 39 40 41 42 43 44 o - g1_txd [7:0] extension gmac1 gmii transmit data output. in 1000mbps gmii mode, g1_txd [7:0] transmitted data is sent synchronously at the rising edge of g1_gtxc. in 10/100mbps mii mode, only g1_txclk [3:0] are available for transmitting and receiving data at the rising edge of g1_txclk. g1_txen 45 o - g1_txen extension gmac1 gmii transmit data enable output. transmit enable that is sent sync hronously at the rising edge of g1_gtxc in gmii mode. transmit enable that is sent sync hronously at the rising edge of g1_txclk in 10/100mbps mii mode. g1_gtxc 47 o - g1_gtxc extension gmac1 gmii transmit clock output. 125mhz transmit clock output when gmii is operating at 1gbps. used to synchronize g1_txd[7:0] and g1_txen. g1_txclk 48 i - g1_txclk 2.5/25mhz transmit clock input when the extension gmac1 gmii interface operates in 10/100 mii mode. 2.5/25mhz clock driven by phy when operating in 10/100mbps mii mode. used to synchronize g1_tx[3:0] and g1_txen. this pin must be pulled low with a 1k ohm resistor when not used. g1_rxclk 50 i - g1_rxclk extension gmac1 gmii receive clock input. in gmii mode: 125mhz receive clock. used to synchronize g1_rxd[7:0], and g1_rxdv. in mii 10/100mbps mode: g1_rxclk is 2.5/25mhz. used to synchronize g1_rxd[3:0], g1_rxdv, and g1_crs. this pin must be pulled low with a 1k ohm resistor when not used. g1_rxdv 51 i - g1_rxdv ex tension gmac1 gmii recei ve data valid input. receive data valid is received synchronously at the rising edge of g1_rxclk in both 1gbps gmii and 10/100mbps mii mac mode. this pin must be pulled low with a 1k ohm resistor when not used. g1_rxd0 g1_rxd1 g1_rxd2 g1_rxd3 g1_rxd4 g1_rxd5 g1_rxd6 g1_rxd7 52 53 54 55 56 57 58 59 i - g1_rxd[7:0] extension gmac1 gmii receive data input. received data is received synchron ously at the rising edge of g1_rxclk. in 10/100mbps mii mode, only g1_rxd[3:0] are available. these pins must be pulled low with a 1k ohm resistor when not used.
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 14 track id: jatr-2265-11 rev. 1.0 7.2.2. rgmii pins the extension gmac0 and extension gmac1 of the RTL8363SB support two rgmii interfaces to connect with an external mac or phy device when register configuration is set to rgmii mode interface. table 5. extension gmac0 rgmii pins pin name pin no. type drive (ma) description rg0_rxd3 rg0_rxd2 rg0_rxd1 rg0_rxd0 68 69 70 71 i - rg0_rxd[3:0] extension gmac 0 rgmii receive data input. received data is received sy nchronously by rg0_rxclk. these pins must be pulled low with a 1k ohm resistor when not used. rg0_rxctl 72 i - rg0_rxctl extension gmac 0 rgmii receive control signal input. the rg0_rxctl indicates rx_dv at the rising of rg0_rxclk and rx_er at the falling edge of rg0_rxclk. at rg0_rxclk falling edge, rg0_ rxctl= rx_dv (xor) rx_er. this pin must be pulled low with a 1k ohm resistor when not used. rg0_rxclk 73 i - rg0_rxclk extension gmac0 rgmii receive clock input. rg0_rxclk is 125mhz @ 1gbps, 25mhz @ 100mbps, and 2.5mhz @ 10mbps. used for rg0_rxd[3:0] and rg0_rxctl synchronization at both rg0_rxclk rising and falling edges. this pin must be pulled low with a 1k ohm resistor when not used. rg0_txclk 75 o - rg0_txclk extension gmac0 rgmii transmit clock output. rg0_txclk is 125mhz @ 1gbps, 25mhz @ 100mbps, and 2.5mhz @ 10mbps. used for rg0_txd[3:0] and rg0_txctl synchronization at rg0_txclk on both rising and falling edges. rg0_txctl 76 o - rg0_txctl extension gmac0 rgmii transmit control signal output. the rg0_txctl indicates tx_en at the rising edge of rg0_txclk, and tx_er at the falling edge of rg0_txclk. at the rg0_txclk falling edge , rg0_txctl= tx_en (xor) tx_er. rg0_txd0 rg0_txd1 rg0_txd2 rg0_txd3 77 78 79 80 o - rg0_txd[3:0] extension gmac0 rgmii transmit data output. transmitted data is sent synchronously to rg0_txclk.
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 15 track id: jatr-2265-11 rev. 1.0 table 6. extension gmac1 rgmii pins pin name pin no. type drive (ma) description rg1_txd3 rg1_txd2 rg1_txd1 rg1_txd0 41 42 43 44 o - rg1_txd[3:0] extension gmac1 rgmii transmit data output. transmitted data is sent synchronously to rg1_txclk. rg1_txctl 45 o - rg1_txctl extension gmac1 rgmii transmit control signal output. the rg1_txctl indicates tx_en at the rising edge of rg1_txclk, and tx_er at the falling edge of rg1_txclk. at the rg1_txclk falling edge , rg1_txctl= tx_en (xor) tx_er. rg1_txclk 47 o - rg1_txclk extension gmac1 rgmii transmit clock output. rg1_txclk is 125mhz @ 1gbps, 25mhz @ 100mbps, and 2.5mhz @ 10mbps. used for rg1_txd[3:0] and rg1_txctl synchronization at rg1_txclk on both rising and falling edges. rg1_rxclk 50 i - rg1_rxclk extension gmac1 rgmii receive clock input. rg1_rxclk is 125mhz @ 1gbps, 25mhz @ 100mbps, and 2.5mhz @ 10mbps. used for rg1_rxd[3:0] and rg1_rxctl synchronization at both rg1_rxclk rising and falling edges. this pin must be pulled low with a 1k ohm resistor when not used. rg1_rxctl 51 i - rg1_rxctl extension gmac 1 rgmii receive control signal input. the rg1_rxctl indicates rx_dv at the rising of rg1_rxclk and rx_er at the falling edge of rg1_rxclk. at rg1_rxclk falling edge, rg1_ rxctl= rx_dv (xor) rx_er. this pin must be pulled low with a 1k ohm resistor when not used. rg1_rxd0 rg1_rxd1 rg1_rxd2 rg1_rxd3 52 53 54 55 i - rg1_rxd[3:0] extension gmac 1 rgmii receive data input. received data is received sy nchronously by rg1_rxclk. these pins must be pulled low with a 1k ohm resistor when not used.
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 16 track id: jatr-2265-11 rev. 1.0 7.2.3. mii pins the extension gmac0 and extensi on gmac1 of the RTL8363SB support two mii interface s to connect with an external mac or phy device when register c onfiguration is set to mii mode interface. these two mii interfaces also can be configured as mii mac mode or mii phy mode by register. table 7. extension gmac0 mii pins (mii mac mode or mii phy mode) pin name pin no. type drive (ma) description m0m_crs 63 i - m0m_crs extension gmac0 mii mac mode carrier sense input when operating in 10/100 mii half duplex mode. this pin must be pulled low with a 1k ohm resistor when not used. m0m_rxd3/ m0p_txd3 m0m_rxd2/ m0p_txd2 m0m_rxd1/ m0p_txd1 m0m_rxd0/ m0p_txd0 68 69 70 71 i - m0m_rxd[3:0] extension gmac0 mii mac mode receive data input. received data that is received sync hronously at the rising edge of m0m_rxclk. m0p_txd[3:0] extension gmac0 mii phy mode transmit data input. transmitted data is received synchronously at the rising edge of m0p_txclk. these pins must be pulled low with a 1k ohm resistor when not used. m0m_rxdv/ m0p_txen 72 i - m0m_rxdv extension gmac0 mii mac mode receive data valid input. receive data valid sent synchron ously at the rising edge of m0m_rxclk. m0p_txen extension gmac0 mii phy mode transmit data enable input. transmit data enable is received sync hronously at the rising edge of m0p_txclk. this pin must be pulled low with a 1k ohm resistor when not used. m0m_rxclk/ m0p_txclk 73 i/o - m0m_rxclk extension gmac0 mii mac mode receive clock input. in mii 100mbps, m0m_rxclk is 25mhz clock input. in mii 10mbps, m0m_rxclk is 2.5mhz clock input. used to synchronize m0m_rxd[3:0], m0m_rxdv, and m0m_crs. m0p_txclk extension gmac0 mii phy mode transmit clock output. in mii 100mbps, m0p_txclk is 25mhz clock output. in mii 10mbps, m0p_txclk is 2.5mhz clock output. used to synchronize m0p_txd[3:0], and m0p_txen. this pin must be pulled low with a 1k ohm resistor when not used. m0m_txclk/ m0p_rxclk 75 i/o - m0m_txclk extension gmac0 mii mac mode transmit clock input. in mii 100mbps, m0m_txclk is 25mhz clock input. in mii 10mbps, m0m_txclk is 2.5mhz clock input. used to synchronize m0m_txd[3:0], and m0m_txen. m0p_rxclk extension gmac0 mii phy mode receive clock output. in mii 100mbps, m0p_rxclk is 25mhz clock output. in mii 10mbps, m0p_rxclk is 2.5mhz clock output. used to synchronize m0p_rxd[3:0], and m0p_rxdv. this pin must be pulled low with a 1k ohm resistor when not used.
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 17 track id: jatr-2265-11 rev. 1.0 pin name pin no. type drive (ma) description m0m_txen/ m0p_rxdv/ 76 o - m0m_txen extension gmac0 mii mac mode transmit data enable output. transmit enable that is sent sync hronously at the rising edge of m0m_txclk. m0p_rxdv extension gmac0 mii phy mode receive data valid output. receive data valid signal that is sent synchronously at the rising edge of m0p_rxclk. m0m_txd0/ m0p_rxd0 m0m_txd1/ m0p_rxd1 m0m_txd2/ m0p_rxd2 m0m_txd3/ m0p_rxd3 77 78 79 80 o - m0m_txd[3:0] extension gmac0 mii mac mode transmit data output. transmitted data is sent synchronously at the rising edge of m0m_txclk. m0p_rxd[3:0] extension gmac0 mii phy mode receive data output. received data is received synchron ously at the rising edge of m0p_rxclk. table 8. extension gmac1 mii pins (mii mac mode or mii phy mode) pin name pin no. type drive (ma) description m1m_crs 36 i - m1m_crs extension gmac1 mii mac mode carrier sense input when operating in 10/100 mii half duplex mode. this pin must be pulled low with a 1k ohm resistor when not used. m1m_txd3/ m1p_rxd3 m1m_txd2/ m1p_rxd2 m1m_txd1/ m1p_rxd1 m1m_txd0/ m1p_rxd0 41 42 43 44 o - m1m_txd[3:0] extension gmac1 mii mac mode transmit data output. transmitted data is sent synchronously at the rising edge of m1m_txclk. m1p_rxd[3:0] extension gmac1 mii phy mode receive data output. received data is received synchron ously at the rising edge of m1p_rxclk. m1m_txen/ m1p_rxdv 45 o - m1m_txen extension gmac1 mii mac mode transmit data enable output. transmit enable that is sent sync hronously at the rising edge of m1m_txclk. m1p_rxdv extension gmac1 mii phy mode receive data valid output. receive data valid signal that is sent synchronously at the rising edge of m1p_rxclk.
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 18 track id: jatr-2265-11 rev. 1.0 pin name pin no. type drive (ma) description m1m_txclk/ m1p_rxclk 47 i/o - m1m_txclk extension gmac1 mii mac mode transmit clock input. in mii 100mbps, m1m_txclk is 25mhz clock input. in mii 10mbps, m1m_txclk is 2.5mhz clock input. used to synchronize m1m_txd[3:0] and m1m_txen. m1p_rxclk extension gmac1 mii phy mode receive clock output. in mii 100mbps, m1p_rxclk is 25mhz clock output. in mii 10mbps, m1p_rxclk is 2.5mhz clock output. used to synchronize m1p_rxd[3:0] and m1p_rxdv. this pin must be pulled low with a 1k ohm resistor when not used. m1m_rxclk/ m1p_txclk 50 i/o - m1m_rxclk extension gmac1 mii mac mode receive clock input. in mii 100mbps, m1m_rxclk is 25mhz clock input. in mii 10mbps, m1m_rxclk is 2.5mhz clock input. used to synchronize m1m_rxd[3:0], m1m_rxdv, and m1m_crs. m1p_txclk extension gmac1 mii phy mode transmit clock output. in mii 100mbps, m1p_txclk is 25mhz clock output. in mii 10mbps, m1p_txclk is 2.5mhz clock output. used to synchronize m1p_txd[3:0] and m1p_txen. this pin must be pulled low with a 1k ohm resistor when not used. m1m_rxdv/ m1p_txen 51 i - m1m_rxdv extension gmac1 mii mac mode receive data valid input. receive data valid sent synchron ously at the rising edge of m1m_rxclk. m1p_txen extension gmac1 mii phy mode transmit data enable input. transmit data enable is received sync hronously at the rising edge of m1p_txclk. this pin must be pulled low with a 1k ohm resistor when not used. m1m_rxd0/ m1p_txd0 m1m_rxd1/ m1p_txd1 m1m_rxd2/ m1p_txd2 m1m_rxd3/ m1p_txd3 52 53 54 55 i - m1m_rxd[3:0] extension gmac1 mii mac mode receive data input. received data that is received sync hronously at the rising edge of m1m_rxclk. m1p_txd[3:0] extension gmac1 mii phy mode transmit data input. transmitted data is received synchronously at the rising edge of m1p_txclk. these pins must be pulled low with a 1k ohm resistor when not used.
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 19 track id: jatr-2265-11 rev. 1.0 7.3. led pins the RTL8363SB led pins can be c onfigured to parallel m ode led or serial mode led interface via register configuration. led 0, led1, and led2 of port n indicate information that can be defined via register or eeprom. in parallel led mode, when the led pin is pulled low, the led output polarity will be high active. when the led pin is pulled high, the led output polarity will change fro m high active to low active. see section 9.19 led indicators, page 37 for more details. table 9. led pins pin name pin no. type drive (ma) description p2led2/ dis_8051 89 i/o pu - port 2 led2 output signal. p2led2 indicates information is defined by register or eeprom. see section 9.19 led indicators, page 37 for more details. p2led1 92 i/o pu - port 2 led1 output signal. p2led1 indicates information is defined by register or eeprom. see section 9.19 led indicators, page 37 for more details. p2led0/ disautoload 91 i/o pu - port 2 led0 output signal. p2led0 indicates information is defined by register or eeprom. see section 9.19 led indicators, page 37 for more details. p1led2/ reserved 93 i/o pu - port 1 led2 output signal. p1led2 indicates information is defined by register or eeprom. see section 9.19 led indicators, page 37 for more details. p1led1 95 i/o pu - port 1 led1 output signal. p1led1 indicates information is defined by register or eeprom. see section 9.19 led indicators, page 37 for more details. p1led0/ reserved 94 i/o pu - port 1 led0 output signal. p1led0 indicates information is defined by register or eeprom. see section 9.19 led indicators, page 37 for more details.
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 20 track id: jatr-2265-11 rev. 1.0 7.4. configuration strapping pins table 10. configuration strapping pins pin name pin no. type description dis_spis 87 i/o pu spi slave management interface selection. pull up: disable spi slave management interface pull down: enable spi slave management interface note: this pin must be kept floating, or pulled high or low via an external 4.7k ohm resistor upon power on or reset. dis_rom 88 i/o pu internal use/reserved. note: this pin must be kept floating, or pulled high via an external 4.7k ohm resistor upon power on or reset. dis_8051 89 i/o pu disable embedded 8051. pull up: disable embedded 8051 pull down: enable embedded 8051 note1: the strapping pin disautoload and dis_8051 are for power on or reset initial stage configuration. refer to table 11 configuration strapping pins (disautoload and dis_8051), page 21 for details. note2: this pin must be kept floating, or pulled high or low via an external 4.7k ohm resistor upon power on or reset. disautoload/ p2led0 91 i/o pu disable eeprom auto-load. pull up: disable eeprom auto-load pull down: enable eeprom/flash auto-load note1: the strapping pin disautoload and dis_8051 are for power on or reset initial stage configuration. refer to table 11 configuration strapping pins (disautoload and dis_8051), page 21 for details. note2: this pin must be kept floating, or pulled high or low via an external 4.7k ohm resistor upon power on or reset. reserved/ p1led2 93 i/o pu internal use/reserved. note: this pin must be kept floating, or pulled high via an external 4.7k ohm resistor upon power on or reset. when pulled high, the led output polarity will be low active. see section 9.19 led indicator, page 37 for more details. reserved/ p1led0 94 i/o pu internal use/reserved. note: for normal operation, this pin must be pulled low via an external 4.7k ohm resistor upon power on or reset. when pulled low, the led output polarity will be high active. see section 9.19 led indicator, page 37 for more details. smi_sel 96 i/o pu eeprom smi/mii management interface selection. pull up: eeprom smi inte rface when dis_spis = 1 pull down: mii management interface when dis_spis = 1 note: this pin must be kept floating, or pulled high or low via an external 4.7k ohm resistor upon power on or reset. reserved 20 i internal use/reserved. note: this pin must be pulled low via an external 4.7k ohm resistor upon power on or reset. reserved 21 i internal use/reserved. note: this pin must be pulled low via an external 4.7k ohm resistor upon power on or reset. reserved 35 i internal use/reserved. note: this pin must be pulled low via an external 4.7k ohm resistor upon power on or reset.
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 21 track id: jatr-2265-11 rev. 1.0 7.5. configuration strapping pins (disautoload and dis_8051) table 11. configuration strapping pins (disautoload and dis_8051) disautoload dis_8051 initial stage (power on or reset) loading data from to 0 eeprom register 0 1 eeprom embedded 8051 instruction memory 1 irrelevant n/a n/a 7.6. management interface pins table 12. management interface pins pin name pin no. type description spis_csi 103 i when dis_spis is pulled low, the spi sl ave management interface is enabled. this pin acts as spi slave mode chip selection input pin. when dis_spis is pulled up, the spi slave management interface is disabled. spis_ck/sck/ mmd_mdc 99 i/o pu when dis_spis is pulled low, the spi sl ave management interface is enabled. this pin acts as spi slave mode serial clock input pin. when dis_spis is pulled up, the spi slave management interface is disabled. this pin act as eeprom smi interface clock/mii management interface clock (selected via the hardware strapping pin, smi_sel). spis_di/sda/ mmd_mdio 102 i/o pu when dis_spis is pulled low, the spi sl ave management interface is enabled. this pin acts as spi slave mode serial data input pin. when dis_spis is pulled up, the spi slave management interface is disabled. this pin act as eeprom smi interface data/mii management interface data (selected via the hardware strapping pin, smi_sel). spis_do 101 o when dis_spis is pulled low, the spi sl ave management interface is enabled. this pin acts as spi slave mode serial data output pin. when dis_spis is pulled up, the spi slave management interface is disabled. interrupt 18 o pu interrupt output for external cpu.
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 22 track id: jatr-2265-11 rev. 1.0 7.7. miscellaneous pins table 13. miscellaneous pins pin name pin no. type description xtalo 97 ao 25mhz crystal clock output pin. 25mhz +/-50ppm tolerance crystal output. xtali 98 ai 25mhz crystal clock input and feedback pin. 25mhz +/-50ppm tolerance crystal reference or oscillator input. mdiref 10 ao reference resistor. a 2.49k ohm (1%) resistor must be connected between mdiref and gnd. reserved 31 ao reserved. must be left floating in normal operation. reserved 32 ao reserved. must be left floating in normal operation. nreset 104 i s system reset input pin. when low active will reset the RTL8363SB. 7.8. test pins table 14. test pins pin name pin no. type description rtt1 12 ao reserved for internal use. must be left floating. rtt2 14 ao reserved for internal use. must be left floating. 7.9. power and gnd pins table 15. power and gnd pins pin name pin no. type description dvddio_0 61, 85 p digital i/o high voltage power for extension port 0 general purpose interface, management interface, and nreset. dvddio_1 46, 60 p digital i/o high voltage power for extension port 1 general purpose interface. dvddio 16 p digital i/o high voltage power for interrupt, dis_lpd/buzzer. dvddl 19, 62, 86 p digital low voltage power. avddh 5, 8, 15, 28, 30, 106, 108, 122 ap analog high voltage power. av d d l 6, 11, 27, 29, 107, 113, 128 ap analog low voltage power. pllvddl0 119 ap pll0 low voltage power. gnd 7, 13, 17, 23, 24, 25, 26, 33, 34, 49, 90, 100, 105, 114, 121, 127 g gnd. agnd 9 ag analog gnd. pllgnd0 120 ag pll0 gnd.
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 23 track id: jatr-2265-11 rev. 1.0 8. physical layer functional overview 8.1. mdi interface the RTL8363SB embeds dual gigabit ethernet phys in one chip. each port uses a single common mdi interface to support 1000base-t, 100bas e-tx, and 10base-t. this interface consists of four signal pairs- a, b, c, and d. each signal pair consists of two bi -directional pins that can transmit and receive at the same time. the mdi interface has internal terminati on resistors, and therefore reduces bom cost and pcb complexity. for 1000base-t, all four pairs are used in both direct ions at the same time. for 10/100 links and during auto-negotiation, only pairs a and b are used. 8.2. 1000base-t transmit function the 1000base-tx transmit function performs 8b/10b coding, scrambling, and 4d-pam5 encoding. these code groups are passed through a waveform-s haping filter to minimize emi effects, and are transmitted onto 4-pair cat5 cable at 125mbaud/s through a d/a converter. 8.3. 1000base-t receive function input signals from the media pass through the sophi sticated on-chip hybrid circuit to subtract the transmitted signal from the input signal for effectiv e reduction of near-end echo. the received signal is then processed with state-of-the -art technology, e.g., adaptive equa lization, blw (baseline wander) correction, cross-talk cancellati on, echo cancellation, timing recover y, error correction, and 4d-pam5 decoding. the 8-bit-wide data is recovered and is se nt to the gmii interface at a clock speed of 125mhz. the rx mac retrieves the packet data from the inte rnal receive mii/gmii inte rface and sends it to the packet buffer manager. 8.4. 100base-tx transmit function the 100base-tx transmit function performs parallel to serial conversion, 4b/5b coding, scrambling, nrz/nrzi conversion, and mlt-3 enc oding. the 5-bit serial data str eam after 4b/5b coding is then scrambled as defined by the tp-pmd stream cipher function to flatten the power spectrum energy such that emi effects can be reduced significantly. the scrambled seed is based on phy addresses and is unique for each port. after scrambling, the bit stream is driven onto the network media in th e form of mlt-3 signaling. the mlt-3 multi-level signaling technology moves the power spectrum energy from high frequency to low frequency, which also reduces emi emissions.
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 24 track id: jatr-2265-11 rev. 1.0 8.5. 100base-tx receive function the receive path includes a receiver composed of an adaptive equalizer and dc restoration circuits (to compensate for an incoming distorted mlt-3 signal0), an mlt-3 to nrzi and nrzi to nrz converter to convert analog signals to digital bit-stream, and a pl l circuit to clock data bi ts with minimum bit error rate. a de-scrambler, 5b/4b decoder, and serial-to-parallel conversion circuits ar e followed by the pll circuit. finally, the converted parallel data is fed into the mac. 8.6. 10base-t transmit function the output 10base-t waveform is manchester-encoded be fore it is driven onto the network media. the internal filter shapes the driven signals to reduce emi emissions, eliminating the need for an external filter. 8.7. 10base-t receive function the manchester decoder converts the incoming serial stream to nrz data when the squelch circuit detects the signal level is above squelch level. 8.8. auto-negotiation for utp the RTL8363SB obtains the states of duplex, speed, and flow control ability for each port in utp mode through the auto-negotiation mechanism defined in the ieee 802.3 specifications. during auto- negotiation, each port advertises its ability to its link partner and compar es its ability with advertisements received from its link partner. by default, the r tl8363sb advertises full capab ilities (1000full, 100full, 100half, 10full, 10half) together with flow control ability.
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 25 track id: jatr-2265-11 rev. 1.0 8.9. crossover detection and auto correction the RTL8363SB automatically determines whether or not it needs to crossover between pairs (see table 16) so that an external crossover cable is not requ ired. when connecting to a nother device that does not perform mdi crossover, when necessary, the rtl 8363sb automatically switches its pin pairs to communicate with the remote device. when connecti ng to another device that does have mdi crossover capability, an algorithm determines whic h end performs the crossover function. the crossover detection and auto correction function can be disabled via regist er configuration. the pin mapping in mdi and mdi crossover mode is given below. table 16. media dependent interface pin mapping pairs mdi mdi crossover 1000base-t 100base-tx 10base-t 1000base-t 100base-tx 10base-t a a tx tx b rx rx b b rx rx a tx tx c c unused unused d unused unused d d unused unused c unused unused 8.10. polarity correction the RTL8363SB automatically corrects polarity errors on the receiver pairs in 1000base-t and 10base-t modes. in 100base-tx mode, the polarity is irrelevant. in 1000base-t mode, receive polarity errors are auto matically corrected based on the sequence of idle symbols. once the de-scrambler is lo cked, the polarity is also locked on all pairs. the polarity becomes unlocked only when the receiver loses lock. in 10base-t mode, polarity errors ar e corrected based on the detection of valid spaced link pulses. the detection begins during the mdi cr ossover detection phase and locks when the 10base-t link is up. the polarity becomes unlocked when the link is down. rx tx + _ + _ tx rx + _ + _ + _ RTL8363SB link partner figure 4. conceptual example of polarity correction
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 26 track id: jatr-2265-11 rev. 1.0 9. general function description 9.1. reset 9.1.1. hardware reset in a power-on reset, an in ternal power-on reset pulse is generate d and the RTL8363SB will start the reset initialization procedures. these are: ? determine various default settings via the hardware strap pins at the end of the nreset signal ? auto-load the configuration from eeprom if eeprom is detected ? complete the embedded sram bist process ? initialize the packet buffer descriptor allocation ? initialize the internal registers and prepar e them to be accessed by the external cpu 9.1.2. software reset the RTL8363SB supports two software rese ts; a chip reset and a soft reset. 9.1.2.1 chip_reset when chip_reset is set to 0b1 (wri te and self-clear), the chip will take the following steps: 1. download configuration from strap pin and eeprom 2. start embedded sram bist (built-in self test) 3. clear all the lookup and vlan tables 4. reset all registers to default values 5. restart the auto-n egotiation process 9.1.2.2 soft_reset when soft_reset is set to 0b1 (wri te and self-clear), the chip will take the following steps: 1. clear the fifo and re-start the packet buffer link list 2. restart the auto-n egotiation process
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 27 track id: jatr-2265-11 rev. 1.0 9.2. ieee 802.3x full duplex flow control the RTL8363SB supports ieee 802.3x flow control in 10/100/1000m modes. flow control can be decided in two ways: ? when auto-negotiation is enabled, flow control depends on the result of nway ? when auto-negotiation is disabled, flow control depends on register definition 9.3. half duplex flow control in half duplex mode, the csma/cd media access met hod is the means by which two or more stations share a common transmission medium. to transmit, a station waits (defers) fo r a quiet period on the medium (that is, no other station is transmitting) and then sends the intended message in bit-serial form. if the message collides with that of another station, then each transmitting station intentionally transmits for an additional predefined period to ensure propagati on of the collision throughout the system. the station remains silent for a random amount of time (b ackoff) before attempting to transmit again. when a transmission attempt has terminated due to a collision, it is retried until it is successful. the scheduling of the retransmissions is determined by a controlled randomization process called ?truncated binary exponential backoff?. at the end of enforcing a collision (jamming), the switch delays before attempting to retransmit the frame. the delay is an integer multiple of slot time (512 bit times). the number of slot times to delay befo re the nth retransmission attempt is chosen as a uniformly distributed random integer ?r? in the range: 0 r < 2k where: k = min (n, backofflimit). the backofflimit for the RTL8363SB is 9. the half duplex back-off algorithm in the rtl8363s b does not have the maximum retry count limitation of 16 (as defined in ieee 802.3). this means packets in the switch will not be dropped if the back-off retry count is over 16. 9.3.1. back-pressure mode in back-pressure mode, the RTL8363SB sends a 4- byte jam pattern (data=0xaa) to collide with incoming packets when congestion c ontrol is activated. th e jam pattern collides at the fourth byte counted from the preamble. the RTL8363SB supports 48pass1, which receives one packet after 48 consecutive jam collisions (data collisions are not incl uded in the 48). enable this function to prevent port partition after 63 consecutive collisions (data collisions + consecutive jam collisions).
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 28 track id: jatr-2265-11 rev. 1.0 9.4. search and learning search when a packet is received, the RTL8363SB uses the destination mac address, filtering identifier (fid) and enhanced fid (efid) to search the 2k-entry look-up table. the 48-bit mac address, 4-bit fid and 3-bit efid use a hash algorithm, to calculate an 11-bit index value. the RTL8363SB uses the index to compare the packet mac address with the entries (mac addresses) in the look -up table. this is the ?address search?. if the destination mac address is not found, the switch will broadcast the packet according to vlan configuration. learning the RTL8363SB uses the source mac address, fid, an d efid of the incoming packet to hash into a 9-bit index. it then compares the source mac address with th e data (mac addresses) in this index. if there is a match with one of the entries, the rt l8363sb will update the entry with new information. if there is no match and the 2k entries are not all o ccupied by other mac addresses, the RTL8363SB will record the source mac address and ingress port number into an empt y entry. this process is called ?learning?. the RTL8363SB supports a 64-entry content addressa ble memory (cam) to avoid look-up table hash collisions. when all 2k entries in the look-up table index are occupie d, the source mac address can be learned into the 64-entry cam. if both the look-up table and the cam are full, the source mac address will not be learned in the RTL8363SB. address aging is used to keep the contents of the address table correct in a dynamic network topology. the look-up engine will update the time stamp info rmation of an entry whenever the corresponding source mac address appears. an entry will be inva lid (aged out) if its time stamp information is not refreshed by the address learning process duri ng the aging time period. the aging time of the RTL8363SB is between 200 and 400 sec onds (typical is 300 seconds). 9.5. svl and ivl/svl the RTL8363SB supports a 16-group filt ering identifier (fid) for l2 se arch and learning. in default operation, all vlan entries belong to the same fid. this is called shared vlan learning (svl). if vlan entries are configured to different fids, th en the same source mac address with multiple fids can be learned into different look- up table entries. this is called independent vlan learning and shared vlan learning (ivl/svl). 9.6. illegal frame filtering illegal frames such as crc error packets, runt packets (length <64 bytes ), and oversize packets (length >maximum length) will be discarded by the RTL8363SB. the maximum packet length may be set to 1522, 1536, 1552, or 16k bytes.
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 29 track id: jatr-2265-11 rev. 1.0 9.7. ieee 802.3 reserved group addresses filtering control the RTL8363SB supports the ability to drop/f orward ieee 802.3 specified reserved group mac addresses: 01-80-c2-00-00-00 to 01 -80-c2-00-00-2f. the default sett ing enables forwarding of these reserved group mac address control frames. fr ames with group mac address 01-80-c2-00-00-01 (802.3x pause) and 01-80-c2-00-00-02 (802.3ad lacp) will always be filtered. table 17 shows the reserved multicast address (rma) configuration mode from 01-80- c2-00-00-00 to 01-80-c2-00-00-2f. table 17. reserved multicast address configuration table assignment value bridge group address 01-80-c2-00-00-00 ieee std 802.3, 1988 editio n, full duplex pause oper ation 01-80-c2-00-00-01 ieee std 802.3ad slow protocols-mu lticast address 01 -80-c2-00-00-02 ieee std 802.1x pae addr ess 01-80-c2-00-00-03 provider bridge group address 1-80-c2-00-00-08 undefined 802.1 address 01-80-c2-00-00-04 ~ 01-80-c2-00-00-07 & 01-80-c2-00-00-09 ~ 01-80-c2-00-00-0c & 01-80-c2-00-00-0f provider bridge mvrp address 01-80-c2-00-00-0d ieee std 802.1ab link layer discovery protocol address 01-80-c2-00-00-0e all lans bridge management group address 01-80-c2-00-00-10 load server generic address 01-80-c2-00-00-11 loadable device generic address 01-80-c2-00-00-12 undefined 802.1 address 01-80-c2-00-00-13 ~ 01-80-c2-00-00-17 & 01-80-c2-00-00-19 & 01-80-c2-00-00-1b ~ 01-80-c2-00-00-1f generic address for all manager stations 01-80-c2-00-00-18 generic address for all agent stations 01-80-c2-00-00-1a gmrp address 01-80-c2-00-00-20 gvrp address 01-80-c2-00-00-21 undefined garp address 01-80-c2-00-00-22 | 01-80-c2-00-00-2f
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 30 track id: jatr-2265-11 rev. 1.0 9.8. broadcast/multicast/unknown da storm control the RTL8363SB enables or disables per-port broa dcast/multicast/unknown da storm control by setting registers (default is disabled). after the receiving rate of broa dcast/multicast/unknown da packets exceeds a reference rate, all other broadcast/mu lticast/unknown da packets will be dropped. the reference rate is set vi a register configuration. 9.9. port security function the RTL8363SB supports three types of secur ity function to preven t malicious attacks: ? per-port enable/disable sa auto-learning for an ingress packet ? per-port enable/disable look-up table agi ng update function for an ingress packet ? per-port enable/disable drop all unknown da packets 9.10. mib counters the RTL8363SB supports a set of count ers to support management functions. ? mib-ii (rfc 1213) ? ethernet-like mib (rfc 3635) ? interface group mib (rfc 2863) ? rmon (rfc 2819) ? bridge mib (rfc 1493) ? bridge mib extension (rfc 2674) 9.11. port mirroring the RTL8363SB supports one set of port mirroring f unctions for all ports. th e tx, or rx, or both tx/rx packets of the source port can be monitored to multiple mirror ports.
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 31 track id: jatr-2265-11 rev. 1.0 9.12. vlan function the RTL8363SB supports 4k vlan groups. these ca n be configured as port-based vlans, ieee 802.1q tag-based vlans, and protocol-based vlans. two ingress-filtering and egress-filtering options provide flexible vlan configuration: ingress filtering ? the acceptable frame type of the ingress process can be set to ?admit all? or ?admit all tagged? ? ?admit? or ?discard? frames associated with a vl an for which that port is not in the member set egress filtering ? ?forward? or ?discard? leaky vlan fr ames between different vlan domains ? ?forward? or ?discard? multicast vlan fr ames between different vlan domains the vlan tag can be inserted or removed at the output port. the RTL8363SB will insert a port vid (pvid) for untagged frames, or remove the tag from tagged frames. the RTL8363SB also supports a special insert vlan tag function to separate tra ffic from the wan and lan sides in router and gateway applications. in router applications, the router may want to know which input port this packet came from. the RTL8363SB supports port vid (pvid) for each port a nd can insert a pvid in the vlan tag on egress. using this function, vid information carried in the vlan tag will be changed to pvid. the RTL8363SB also provides an option to admit vlan ta gged packets with a specific pvid only. if this function is enabled, it will drop non-tagged p ackets and packets with an incorrect pvid. 9.12.1. port-based vlan this default configuration of the vlan function can be modified via an attached serial eeprom or eeprom smi slave interface. the 4k-entry vlan ta ble designed into the RTL8363SB provides full flexibility for users to co nfigure the input ports to associate with different vlan groups. each input port can join with more than one vlan group. port-based vlan mapping is the simplest implicit ma pping rule. each ingress packet is assigned to a vlan group based on the input port. it is not necessa ry to parse and inspect frames in real-time to determine their vlan association. all the packets re ceived on a given input port will be forwarded to this port?s vlan members. 9.12.2. ieee 802.1q tag-based vlan the RTL8363SB supports 4k vlan entries to pe rform 802.1q tag-based vlan mapping. in 802.1q vlan mapping, the RTL8363SB uses a 12-bit explicit id entifier in the vlan tag to associate received packets with a vlan. the RTL8363SB compares the ex plicit identifier in th e vlan tag with the 4k vlan table to determine the vlan association of this packet, and then forwards this packet to the member set of that vlan. two vids are reserved for special purposes. one of them is all 1?s, which is reserved and currently unused. the other is all 0?s, wh ich indicates a priority tag. a priority-tagged frame should be treated as an untagged frame. when ?802.1q tag aware vlan? is enabled, the RTL8363SB performs 802.1q tag-based vlan mapping for tagged frames, but still performs port -based vlan mapping for untagged frames. if ?802.1q
RTL8363SB datasheet layer 2 managed 2+2-port 10/100/1000m switch controller 32 track id: jatr-2265-11 rev. 1.0 tag aware vlan? is disabled, the RTL8363SB pe rforms only port-base d vlan mapping both on non- tagged and tagged frames. the processing flow when ?802.1q tag aware vlan? is enabled is illustrated below. two vlan ingress filtering function s are supported in registers by the RTL8363SB. one is the ?vlan tag admit? control, which provides the ability to receive vlan-tagged frames only. untagged or priority tagged (vid=0) frames will be dropped. the other is ?vlan member set ingre ss filtering?, which will drop frames if the ingress port is not in the member set. 9.12.3. protocol-based vlan the RTL8363SB supports a 4-group pr otocol-based vlan conf iguration. the packet format can be rfc 1042, llc, or ethernet, as shown in figure 5. there are 4 configuration tables to assign the frame type and corresponding field value. taking ip packet confi guration as an example, the user can configure the frame type to be ?ethernet?, and value to be ?0x0800?. each table will index to one of the entries in the 4k-entry vlan table. the packet stream will match the protocol type and the value will follow the vlan member configuration of the inde xed entry to forward the packets. figure 5. protocol-based vlan frame format and flow chart 9.12.4. port vid in a router application, the rout er may want to know which input port this packet came from. the RTL8363SB supports port vid (pvid) for each port to insert a pvid in the vlan tag for untagged or priority tagged packets on egress. when 802.1q tag- aware vlan is enabled, vlan tag admit control is enabled, and non-pvid discard is enabled at the sa me time. when these f unctions are enabled, the RTL8363SB will drop non-tagged packets a nd packets with an incorrect pvid.

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